To manufacture a leads-over-chip (LOC) semiconductor device such as a memory device, a microprocessor, or logic device, a front circuit side of a semiconductor die is attached to a lead frame using various adhesives such as double sided tape. Various LOC and backside attach designs are described in U.S. Pat. Nos. 5,140,404; 5,177,032; 5,256,598; 5,304,842, each assigned to Micron Technology, Inc. and U.S. Pat. No. 4,862,245 assigned to International Business Machines Corp. A ceramic LOC assembly is described in U.S. Pat. No. 5,107,328, also assigned to Micron Technology, Inc. Each of these patents is incorporated herein by reference.
To successfully manufacture a semiconductor device having an LOC design, thermal coefficients of expansion (TCE) of the die, the lead frame, and the attach material must closely match. A TCE mismatch between the three components can damage the die if there is a thermal mismatch between the attach material and the die, or can cause the die to separate from the lead frame if there is a TCE mismatch between the attach material and the lead frame.
A semiconductor assembly which reduces problems associated with thermal mismatch would be advantageous.